1. Field of the Invention
The invention relates to a method of fabricating multilevel interconnections of a semiconductor device, and more particularly to a method of fabricating a via and an interconnection.
2. Description of the Related Art
As the integration of semiconductors is enhanced, the dimensions of devices cannot supply enough area for interconnection. To match the requirements of the metal oxide semiconductor (MOS) devices with smaller dimensions, designs of multilevel interconnections are adapted in most of the integrated circuits (ICs). Normally, an inter-metal dielectric (IMD) layer is used to isolate two conductive layers. By the formation of a via plug, the conductive layers are electrically connected.
There are two conventional methods of fabricating a via and an interconnection. One is to fabricate a via and an interconnection in two steps. That is, a dielectric layer is formed on a metal layer first. Using an etching technique to form a via hole, and a via plug is formed by filling the via hole with conductive material. Another metal layer is formed and defined. An inter-metal dielectric layer is then deposited. Another method is to use damascene technique. A via and an interconnection is formed simultaneously. Two steps to define photo-resist are required in the conventional damascene technique. The process is very complicated and is described as follows.
Referring to FIG. 1A to FIG. 1I, processes of conventional damascene technique are shown. Referring to FIG. 1A, a first metal layer 12 is formed on a substrate 10 comprising a metal oxide semiconductor (MOS) device. An inter-metal dielectric layer 14 is formed on the metal layer.
Referring to FIG. 1B, a first photo-resist layer 16 is formed and defined to expose a predetermined region of a via. Referring to FIG. 1C, a second photo-resist layer 26 is formed and defined on the first photo-resist layer 16 to expose a predetermined region of an interconnection. The material of the first photo-resist layer 16 and the material of inter-metal dielectric layer 14 are similar, whereas, the material of the second photo-resist layer 26 is different from the material of the inter-metal dielectric layer 14. Thus, the etching rate of the first photo-resist layer 16 is similar to the etching rate of the inter-metal dielectric layer 14, whereas, the etching rate of the second photo-resist layer 26 is slower than the etching rate of the inter-metal dielectric layer.
Referring to FIG. 1D, using the first photo-resist layer 16 as a mask, the inter-metal dielectric layer 14 is dry etched to form a prototype of a via hole. Meanwhile, using the second photo-resist layer 26 as a mask, the first photo-resist layer 16 is etched to expose the inter-metal dielectric layer 14. The first photo-resist layer 16 and the second photo-resist layer 26 are then combined into one photo-resist layer 36.
Referring to FIG. 1E, using the combined photo-resist layer 36 as a mask, a dry etching step is performed continuously until the via hole a and the interconnection window b are formed to expose the first metal layer 12.
Referring to FIG. 1F, after removing the first photo-resist layer 36, a thin barrier layer 18 conformal to the inter-metal dielectric layer 14 is formed over the substrate. The formation of the barrier layer 18 enhances the adhesion between the subsequent deposited metal and other materials.
Referring to FIG. 1G, a metal layer 22 is formed and fills the via hole a and the interconnection window b shown on FIG. 1E. Using chemical-mechanical polishing (CMP), a step of etching back is performed until parts of the inter-metal dielectric layer 14 are exposed. The exposed parts of the inter-metal dielectric 14 are noted as isolation regions c. A via plug 22a and an interconnection 22b are formed as shown on FIG. 1H. Referring to FIG. 1I, by repeating the steps shown on FIG. 1A to FIG. 1G, another level of interconnections is formed.
As described above, in the conventional damascene, a via and an interconnection are formed at the same time. Two steps of photolithography process are required to define two different levels of photo-resist layers. Therefore, the process is very complicated.